1. Field of the Invention
The present invention relates to a method of fabricating a memory cell, and more particularly to a method of fabricating a non-volatile memory cell.
2. Description of the Related Art
In a variety of non-volatile memories, electrically erasable programmable read-only memory (EEPROM) can perform multiple storing, read/write and erasing functions and the data stored therein will not be erased even if the power is shut down. Therefore, it has been a memory device widely used in personal computers and electronic apparatuses. The typical EEPROM uses polysilicon as a floating gate and a control gate. When the memory is programmed, electrons injected into the floating gate will uniformly spread out therein. However, when defects exist in the tunneling oxide beneath the polysilicon floating gate, leakage currents occur and affect the reliability of the device.
In order to resolve the leakage-current issue of EEPROM, a charge trapping layer is used to replace the polysilicon floating gate. The material of the charge trapping layer can be, for example, silicon nitride. Usually, there are two silicon oxide layers on and under the silicon nitride charge trapping layer for forming a stacked structure with an oxide-nitride-oxide (ONO) layer. The memory cell having the stacked structure is called a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.
FIG. 1 is a figure showing a prior art SONOS memory cell. Please referring to FIG. 1, a ONO layer 102, which is composed of a bottom silicon oxide layer 104, a silicon nitride layer 106 and a top silicon oxide layer 108, is formed on a substrate 100. In addition, a polysilicon gate 112 is formed on the ONO layer 102, serving as a word line. The source/drain regions 118 are formed in the substrate 100 adjacent to the edges of the ONO layer 102, serving as buried bit lines. Moreover, spacers 116 are formed on the sidewalls of the polysilicon gate 112. Lightly doped regions 114 electrically connect with source/drain regions 118 in the substrate 100 beneath the spacers 116.
The prior art SONOS memory cell can perform forward read and reverse read by storing electrons in the right side or left side of the charge trapping layer. The difference of threshold voltages between the programmed cells for forward read and reverse read depends on the quantity and area of the trapped electrons. However, by the increase of the programming times, the difference of threshold voltages for forward read and reverse read will gradually be reduced. The trapped electrons in one side of the charge trapping layer will move to the other side. It results in programming failures. The failures will be more serious when size of devices shrinks.
Therefore, U.S. Pat. No. 6,538,292 discloses a flash memory device with a twin bit cell. The difference between the U.S. patent and the structure in FIG. 1 is that the former uses a polysilicon germanium layer as the electron trapping layer. An ion implantation process is performed to form an isolation area in the polysilicon germanium layer for dividing the polysilicon germanium layer into two discontinuous conductive areas as a twin bit cell structure. Because the isolation area is formed by ion implantation, misalignment arises so that the conductive areas on the drain side and source side have different sizes. That will affect the performance of the memory cell.
U.S. Pat. No. 6,639,271 discloses another method for forming dual bit nitride memory cell. The isolation barrier between the charge trapping layers is formed by sequentially depositing a oxide layer, an isolation barrier dielectric layer, a top dielectric layer and a polysilicon layer on a substrate; patterning these layers; and etching a portion of isolation barrier dielectric layer for forming a undercut isolation barrier dielectric layer. Then, silicon nitride spacers are formed on the sidewalls of the stacked structure composed of the oxide layer, the undercut isolation barrier dielectric layer, the top dielectric layer and the polysilicon layer. The silicon nitride spacers fill in the undercut regions of the isolation barrier dielectric layer for forming electron trapped regions. However, the silicon nitride spacers formed by the prior art method may directly contact the substrate and the polysilicon layer. That will cause the operational problems of the memory device.